Integrated circuit (semiconductor) memory devices include dynamic random access memory (DRAM) devices, static random access memory (SRAM) devices, flash memory devices, etc. In addition, the memory devices may be classified as volatile memory devices or non-volatile memory devices. The non-volatile memory devices may retain their data even though power is off. On the other hand, the volatile memory devices may lose their data when power is off. The non-volatile memory devices, such as a flash memory devices, have been widely employed in digital cameras, MP3 (MPEG audio layer-3) players and cellular phones, etc.
Non-volatile memory devices using a resistive material include, for example, a resistive random access memory (RRAM), a phase change RAM (PRAM), and a magnetic RAM (MRAM). While a dynamic RAM or a flash memory uses charge to store data, the non-volatile memory device using the resistive material stores data using a variation in the resistance of a variable resistive material (RRAM), a variation in the state of a phase change material (PRAM), such as a chalcogenide alloy, or a variation in the resistance of a magnetic tunnel junction (MTJ) thin film according to the magnetization state of a ferromagnetic substance (MRAM).
A resistive memory cell generally includes a first electrode, a second electrode, and a variable resistive material interposed therebetween, and the resistance level of the variable resistive material varies according to a voltage applied between the first and second electrodes.
A PRAM device may include a phase changeable material layer. When heat is applied to the phase changeable material layer, the phase changeable material layer may change its phase so that a resistance in the phase changeable material layer may vary. Generally, the phase changeable material layer may be formed using a chalcogenide compound including germanium (Ge), antimony (Sb) and/or tellurium (Te). Current applied to the phase changeable material layer through an electrode may generate the heat for changing a phase of the phase changeable material layer. The phase of the phase changeable material layer may vary depending on the amount of current and/or a time for which the current is provided. The resistance of the phase changeable material layer may vary in accordance with a state of the phase changeable material layer. Particularly, when the phase changeable material layer has a crystalline state, the resistance of the phase changeable material layer may be relatively small. On the other hand, when the phase changeable material layer has an amorphous state, the resistance of the phase changeable material layer may be relatively large. As a result, the PRAM device including the phase changeable material layer may be employed as a logic device by using a difference in resistance.
Phase changeable memory devices are disclosed in U.S. Pat. No. 6,987,467 to Doan et al., entitled “Controllable Ovanic Phase-Change Semiconductor Memory Device”, U.S. Patent Application Publication No. 2005/0227496 to Park et al., entitled “Phase Change Memory Elements and Methods of Fabricating Phase Change Memory Elements Having a Confined Portion of Phase Change Material on a Recessed Contact”, and Korean Patent Laid-Open Publication No. 10-2006-0001105 to Chang, entitled “Phase-Change Memory Device and Fabricating Method Thereof to Reduce Area of Contact Surface Between Phase-Change Layer Pattern and Upper/Lower Electrode.
FIGS. 1A to 1E are cross-sectional views illustrating a conventional method of manufacturing a phase changeable memory device.
Referring to FIG. 1A, an insulating interlayer 10 is formed on a semiconductor substrate 5 by using an oxide. A contact hole exposing a predetermined portion of the substrate 5 may be then formed by etching the insulating interlayer 10.
A first conductive layer is formed on the insulating interlayer 10 to fill up the contact hole. A pad 15 making contact with the predetermined portion of the substrate 5 may be then formed by partially removing the first conductive layer until the insulating interlayer 10 is exposed.
A second insulating layer 25 and a first insulating layer 20 are formed and subsequently etched by a photolithography process so that an opening 30 exposing the pad 15 may be formed.
Referring to FIG. 1B, a third insulating layer is formed on the exposed pad 15, sidewalls of the opening 30 and the second insulating layer 25. The third insulating layer may be then etched by an anisotropic etching process so that a preliminary spacer 35 may be formed on the sidewalls of the opening 30. The preliminary spacer 35 may be formed using a nitride. Thus, a lower width of the opening 30 may become smaller than an upper width of the opening 30 because the preliminary spacer 35 is formed on the sidewalls of the opening 30.
A second conductive layer 40 is formed on the pad 15 and the second insulating layer 25 to fill up the opening 30. The second conductive layer 40 may be formed using a metal nitride such as titanium nitride or titanium aluminum nitride.
Referring to FIG. 1C, the second conductive layer 40 is polished by a chemical mechanical polishing (CMP) process until the second insulating layer 25 is exposed. Thus, a preliminary lower electrode 45 filling up the opening may be formed on the pad 15.
The second insulating layer 25 is removed by an etch-back process so that upper portions of the preliminary lower electrode 45 and the preliminary spacer 35 are exposed over the first insulating layer 20. As described above, the lower width of the opening 30 is smaller than the upper width of the opening 30. As a result, a lower width of the preliminary lower electrode 45 filling up the opening 30 may be smaller than an upper width of the preliminary lower electrode 45.
Referring to FIG. 1D, upper portions of the preliminary lower electrode 45 and the preliminary spacer 35 protruded upwardly from the first insulating layer 20 are removed by the CMP process so that a lower electrode 50 and a spacer 55 may be formed on the pad 15. Heights of the lower electrode 50 and the spacer 55 may be substantially the same as that of the first insulating layer 20.
Referring to FIG. 1E, a phase changeable material layer and a third electrode layer are formed on the lower electrode 50, the spacer 55 and the first insulating layer 20. Thereafter, the phase changeable material layer and the third electrode layer are patterned so that a phase changeable material layer pattern 60 and an upper electrode 65 may be formed.